`include "common.svh"

module rv_decoder_test (
    input [31:0] inst,
    output logic signed [31:0] dop_imm32,
    output logic [4:0] dop_rs1,
    output logic [4:0] dop_rs2,
    output logic [4:0] dop_rd,
    output logic dop_has_rd,
    output BranchType dop_branch_type,
    output FU_OP dop_fu_op,
    output FU_Type dop_fu_type,
    output logic dop_flush_pipeline,
    output logic dop_is_op32,
    output logic dop_has_imm,
    output logic dop_illegal_inst

);
  DecodeOP dop;

  assign dop_imm32 = dop.imm32;
  assign dop_rs1 = dop.rs1;
  assign dop_rs2 = dop.rs2;
  assign dop_rd = dop.rd;
  assign dop_has_rd = dop.has_rd;
  assign dop_branch_type = dop.branch_type;
  assign dop_fu_op = dop.fu_op;
  assign dop_fu_type = dop.fu_type;
  assign dop_flush_pipeline = dop.flush_pipeline;
  assign dop_is_op32 = dop.is_op32;
  assign dop_has_imm = dop.has_imm;
  assign dop_illegal_inst = dop.illegal_inst;
  rv_decoder inst_decoder (.*);
endmodule

